In a conventional computer based on von Neumann architecture, a program stored in a memory is executed while continuing to access data stored in the memory. With the improvement in computer performance, evolution and development have been made in the form of raising an importance on parallel processing to overcome a bottleneck of data processing speed. However, since there is a limitation in processing a large amount of data that increases geometrically, there is a need to develop a new type of microprocessor.
Neurons and synapses connected in parallel enable a human neutral network to simultaneously perform memorization, operation, and inference with low power. Thus, the human neural network is capable of performing higher-level application processing than a computer based on von Neumann architecture. A neuromorphic technology is a technology for mimicking such a human neural network to hardware based on CMOS integrated circuit technology.
However, a current neuromorphic technology encounters difficulties in integrating large-scale neurons and synapses and implementing a learning function of neurons based on an existing CMOS process. To implement the learning function, a separate processor for controlling a leaning operation is required outside a chip, which serves as a great restriction for commercialization. Accordingly, there is a need to develop a logic device that utilizes an existing CMOS process but makes a new type of memorization possible.
U.S. Pat. No. 5,612,563 discloses a logic device using a vertical MOS transistor. However, U.S. Pat. No. 5,612,563 cannot provide a logic device that memorizes a previous sate because previous state data is lost when an input signal is removed at a gate electrode.